The present invention relates to an analog video signal display unit, and, in particular, to a transmission device for analog video signal and method therefor, which serve for high quality display in a liquid crystal display monitor using a liquid crystal panel. Further, the present invention relates to an image display system, in which video signal and sync signal are transmitted from a video signal output device to a display unit, to be displayed there.
In a conventional technique, as the image display system that transmits video signal and sync signal from a video signal output device to a display unit for displaying there, there is known one comprising a graphics card mounted in a computer unit and a liquid crystal display monitor.
FIG. 18 shows a configuration of such a conventional image display system.
In the figure, a reference numeral 24 refers to a liquid crystal display monitor, and 1 to a graphics card mounted in a computer unit.
Here, the graphics card 1 comprises a video memory 3 and a graphics controller 2.
The graphics controller 2 comprises a memory control circuit 5 for controlling read and write of display data from and into the video memory 3, a reference clock generator 4 for generating, from a prescribed system clock 10, a clock 11 which is to be a reference for operation of the graphics controller 2, a sync signal generator 9 for generating, from the clock 11, vertical sync signal 21 and horizontal sync signal 22, and D-A converters 6, 7, 8 for converting the display data read from the video memory 3 to analog video signals being synchronized with the clock 11. In such a configuration, the graphics controller 2 sequentially reads the display data stored in the video memory 3, in synchronization with the vertical sync signal 21 and horizontal sync signal 22. Then, it converts them in the D-A converters 6, 7, 8, and outputs them as the analog video signals 18, 19, 20. On the other hand, the liquid crystal display monitor 24 comprises A-D converters 28, 29, 30 for converting analog video signals 18, 19, 20 to digital video signals 32, 33, 34, a PLL 27 for generating, from the horizontal sync signal 22, a conversion clock 31 for the A-D converters 28, 29, 30, a liquid crystal display controller 25, and a liquid crystal display unit 26.
In such a configuration, sampling is carried out on the analog video signals 18, 19, 20 inputted from the graphics card 1, in synchronization with the conversion clock 31 generated by the PLL 27, to convert them into digital video signals 32, 33, 34. The liquid crystal display controller 25 displays the digital video signals 32, 33, 34 on the liquid crystal display unit 26, synchronizing them with the horizontal sync signal 22 and vertical sync signal 21.
An example of timing for each signal outputted from the graphics card 1 to the liquid crystal display monitor 24 is shown in FIG. 19.
FIG. 19 is a timing chart showing relationship between the horizontal sync signal 22, the video signals 18, 19, 20, and the clock 11. One horizontal interval for the analog video signals (interval for outputting the video signals corresponding to one display line) comprises a display effective interval and a fly-back interval. The analog video signals and horizontal sync signal are synchronized with the clock 11, and, in a case where a display resolution is 1024 dots in the horizontal direction, the display effective interval corresponds to 1024 clocks, and the fly-back interval corresponds to 304 clocks. Thus, one horizontal interval corresponds to 1328 clocks in total.
On the other hand, in the liquid crystal display monitor 24, the PLL 27 generates the conversion clock 31 synchronized in phase with the horizontal sync signal 22. As shown in FIG. 20, this conversion clock 31 is generated as 1328 clocks for a single period of horizontal sync signal 22. The conversion clock 31 is inputted into the A-D converters 28, 29, 30 to convert the analog video signals 18, 19, 20 to the digital video signals 32, 33, 34. Then, the digital video signals 32, 33, 34 are converted by the liquid crystal display controller 25, into liquid crystal display data 35 to be displayed with liquid crystal, and the liquid crystal display unit 26 displays the image.
In the image display system of such configuration as shown in FIG. 18, it is necessary that the clock 11 generated by the reference clock generator 4 of the graphics card 1 and the conversion clock 31 generated by the PLL 27 of the liquid crystal display monitor 24 coincide to some extent with each other in their phases. When the phases of both clocks deviate largely from each other in their phases, it becomes impossible that the video signals 18, 19, 20 which are made to be analog in the D-A converters 6, 7, 8 being synchronized with the clock 11 are correctly converted in the A-D converters 28, 29, 30 in synchronization with the conversion clock 31. In other words, as shown in FIG. 21C, in A-D conversion, the video signals 18, 19, 20 should be properly converted at a flat portion of their signal waveform AD. However, when phase difference .delta. between both clocks becomes larger, A-D conversion of the video signals 18, 19, 20 are carried out at a portion deviated from the flat portion of the signal waveform, as shown in FIG. 21D. This results in A-D conversion error, which then produces flicker of the display.
However, as the resolution of the liquid crystal display monitor 24 becomes higher, or, in other words, as the frequencies of the clock 11 and conversion clock 31 become higher, it becomes more difficult to make the phases of both clocks coincide with each other owing to problems related to the precision of the clock 11.
Namely, it is inevitable anyway that the period of the clock 11 generated by the reference clock generator 4 varies very slightly for each period, owing to effects of noises from other digital circuits and owing to problems related to the performance etc. On the other hand, the PLL 27 of the liquid crystal display monitor 24 generates the conversion clock 31 as a clock synchronized in phase with the horizontal sync signal 22, whose period is a single horizontal interval. Even if the PLL 27 is ideal one, it is impossible to make the phase of the conversion clock 31 follow up the clock 11 in its phase fluctuation in a single horizontal interval.
For that reason, the phase difference 6 between the clock 11 and the conversion clock 31 varies within a single horizontal interval as shown in FIG. 21B. When the liquid crystal display monitor 24 has high resolution, the phase difference .delta. determined relatively as deviation between clock periods becomes large. This produces flicker of the display owing to the above-described A-D conversion error.
On the other hand, when the graphics card 1 transmits the clock 11 to the liquid crystal display monitor 24, and the liquid crystal display monitor 24 uses it as the conversion clock 31, it is possible to prevent occurrence of such phase difference .delta.. In that case, however, in addition to transmission lines for transmitting the video signals 18, 19, 20 and the sync signals, another transmission line for transmitting the clock is required.
Further, in the conventional image display system, for transmitting audio signal and various setting information for the display unit from the video signal output device to the display unit, respective dedicated transmission lines are required. Thus, there has been such a problem that the number of transmission lines connecting both devices increases, and it brings complexity, also.